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@ -35,7 +35,9 @@
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#define STM32_DMA_STREAM_ID(peripheral, channel) GD32_DMA_STREAM_ID(peripheral - 1, channel - 1)
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#define STM32_DMA_STREAM_ID(peripheral, channel) GD32_DMA_STREAM_ID(peripheral - 1, channel - 1)
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#define STM32_DMA_CR_DIR_M2P GD32_DMA_CTL_DIR_M2P
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#define STM32_DMA_CR_DIR_M2P GD32_DMA_CTL_DIR_M2P
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#define STM32_DMA_CR_PSIZE_WORD GD32_DMA_CTL_PWIDTH_WORD
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#define STM32_DMA_CR_PSIZE_WORD GD32_DMA_CTL_PWIDTH_WORD
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#define STM32_DMA_CR_PSIZE_HWORD GD32_DMA_CTL_PWIDTH_HWORD
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#define STM32_DMA_CR_MSIZE_WORD GD32_DMA_CTL_MWIDTH_WORD
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#define STM32_DMA_CR_MSIZE_WORD GD32_DMA_CTL_MWIDTH_WORD
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#define STM32_DMA_CR_MSIZE_BYTE GD32_DMA_CTL_MWIDTH_BYTE
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#define STM32_DMA_CR_MINC GD32_DMA_CTL_MNAGA
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#define STM32_DMA_CR_MINC GD32_DMA_CTL_MNAGA
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#define STM32_DMA_CR_CIRC GD32_DMA_CTL_CMEN
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#define STM32_DMA_CR_CIRC GD32_DMA_CTL_CMEN
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#define STM32_DMA_CR_PL GD32_DMA_CTL_PRIO
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#define STM32_DMA_CR_PL GD32_DMA_CTL_PRIO
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